A 16-Bit High-Speed Multiplier Design Based on Karatsuba Algorithm and Urdhva-Tiryagbhyam Theorem Using Modified Gdi Cells for Low Power and Area Constraints
ICTACT Journal on Microelectronics
doi 10.21917/ijme.2017.0071
Full Text
Open PDFAbstract
Available in full text
Date
July 1, 2017
Authors
Publisher
ICT Academy