Amanote Research

Amanote Research

    RegisterSign In

Implementation of Multi - Priority and Variable - Length DRRM Scheduling Algorithm Based on FPGA

doi 10.1063/1.5005272
Full Text
Open PDF
Abstract

Available in full text

Date

January 1, 2017

Authors
Hui XuXue SunSuzhi CaoYueying Zhan
Publisher

Author(s)


Related search

Scheduling of a LQ Control Algorithm for Efficient FPGA Implementation

IFAC Proceedings Volumes
2008English

An Implementation of the Run-Length Decode Algorithm Using FPGA

The International Conference on Electrical Engineering
2006English

Multi-Level Security Task Scheduling Scheme Based on Task Priority

2019English

Message Based Random Variable Length Key Encryption Algorithm

Journal of Computer Science
Computer NetworksSoftwareArtificial IntelligenceCommunications
2009English

An Energy-Efficient Fault-Tolerant Scheduling Algorithm Based on Variable Data Fragmentation

IFIP Advances in Information and Communication Technology
Computer NetworksInformation SystemsManagementCommunications
2015English

A New Priority-Sort Based Optimization Algorithm for Integrated Process Planning and Scheduling

International Journal of Modeling and Optimization
2013English

An Efficient FPGA Implementation of AES Algorithm

International Journal of Engineering Research and
2016English

Design and Implementation of Improved NCO Based on FPGA

2019English

Multi-Dimensional Constrained Cloud Computing Task Scheduling Mechanism Based on Genetic Algorithm

International Journal of Online Engineering
EngineeringE-learning
2013English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy