Computation of Field Programmable Cyclic Redundancy Checks Circuit Architecture

International Journal on Smart Sensing and Intelligent Systems - New Zealand
doi 10.21307/ijssis-2017-267
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Exeley, Inc.

Related search

A Two-Step Computation of Cyclic Redundancy Code CRC-32 for ATM Networks

IBM Journal of Research and Development
Computer Science
1997English

Analog Programmable Circuit Implementation for Memristor

Iraqi Journal for Electrical and Electronic Engineering
2018English

Circuit Implementation of a High-Speed Continuous-Time Current-Mode Field Programmable Analog Array (FPAA)

2000English

Field - Programmable Gate Array

2017English

Field-Programmable Silicon Temporal Cloak

Nature Communications
AstronomyGeneticsMolecular BiologyBiochemistryChemistryPhysics
2019English

Increasing Reliability of Programmable Mixed-Signal Systems by Applying Design Diversity Redundancy

2010English

On-The-Fly Computation Method in Field-Programmable Gate Array for Analog-To-Digital Converter Linearity Testing

Journal of Engineering and Technological Sciences
Engineering
2018English

An Architecture for Carrier Grade Programmable Networks

English

Guest Editorial: Field-Programmable Technology

Journal of Signal Processing Systems
ControlSystems EngineeringInformation SystemsSignal ProcessingSimulationHardwareArchitectureModelingTheoretical Computer Science
2011English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy