Formal Proof of the Dependable Bypassing Routing Algorithm Suitable for Adaptive Networks on Chip QnoC Architecture

Systems
doi 10.3390/systems5010017
Full Text
Abstract

Available in full text

Date
Authors
Publisher

MDPI AG

Related search

Low Cost Fault-Tolerant Routing Algorithm for Networks-On-Chip

Microprocessors and Microsystems
Computer NetworksHardwareCommunicationsArchitectureArtificial IntelligenceSoftware
2015English

Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-On-Chip

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2014English

Cluster Based Hierarchical Routing Algorithm for Network on Chip

Circuits and Systems
2013English

Multilevel Full-Chip Routing for the X-Based Architecture

2007English

An Adaptive Distance Vector Routing Algorithm for Mobile, Ad Hoc Networks

English

Research of an Adaptive Aggregation Routing Algorithm in Wireless Sensor Networks

Journal of Networks
2012English

An Adaptive State-Aware Routing Algorithm for Data Aggregation in Wireless Sensor Networks

Journal of Communications
Electronic EngineeringElectrical
2013English

Chip Architecture for Data Sorting Using Recursive Algorithm

Journal of Technology Management for Growing Economies
2010English

Joint Multicast Routing and Network Design Optimisation for Networks-On-Chip

IET Computers and Digital Techniques
HardwareElectronic EngineeringElectricalArchitectureSoftware
2009English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy