Using Hardware Counter-Based Performance Model to Diagnose Scaling Issues of HPC Applications

Neural Computing and Applications - United Kingdom
doi 10.1007/s00521-018-3496-z
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Springer Science and Business Media LLC

Related search

A Feature Selection Model Based on High-Performance Computing (HPC) Techniques

International Journal of Computer Applications
2017English

Performance Evaluation of a Tape-Wound Core Transformer Using Meta-Model Based Scaling Laws

International Journal of Computing and Digital Systems
Computer GraphicsHuman-Computer InteractionComputer NetworksCommunicationsInformation SystemsComputer-Aided DesignInnovationManagement of TechnologyArtificial Intelligence
2017English

Non-Determinism and Overcount on Modern Hardware Performance Counter Implementations

2013English

Model-Based Performance Instrumentation of Distributed Applications

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2008English

Hardware Efficient Scaling Free Vectoring and Rotational Cordic for DSP Applications

International Journal of VLSI Design & Communication Systems
2013English

Using Hardware Counters to Automatically Improve Memory Performance

English

Predictive Simulation of HPC Applications

2009English

Hardening Strategies for HPC Applications

2019English

Deduplication Potential of HPC Applications’ Checkpoints

2016English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy