Amanote Research

Amanote Research

    RegisterSign In

Implementation of Delay and Power Monitoring Schemes to Reduce the Power Consumption

International Journal of Computer Applications
doi 10.5120/2599-3613
Full Text
Open PDF
Abstract

Available in full text

Date

May 31, 2011

Authors
Author Pavan.T.K.Jagannadha Naidu. KNagaraju. V
Publisher

Foundation of Computer Science


Related search

Optimizing Power Consumption, Area, and Delay in Behavioral Synthesis.

English

Ways to Reduce Power Losses in Mining Power Supply Lines

Mining science and technology
2019English

On Smartphone Power Consumption in Acoustic Environment Monitoring Applications

Applied System Innovation
2018English

Classifying Sensors Depending on Their IDs to Reduce Power Consumption in Wireless Sensor Networks

International Journal of Online Engineering
EngineeringE-learning
2010English

Using Asymmetric Cores to Reduce Power Consumption for Interactive Devices With Bi-Stable Displays

2014English

Implementation of Data Encoding Schemes for Power Reduction in Network on Chip Links

International Journal of Recent Trends in Engineering and Research
2018English

A Novel Approach to Minimize Spare Cell Leakage Power Consumption During Physical Design Implementation

International Journal of VLSI Design & Communication Systems
2011English

The Research on Path of Power Industry to Reduce Haze

DEStech Transactions on Computer Science and Engineering
2018English

Using Architecture Information and Real-Time Resource State to Reduce Power Consumption and Communication Costs in Parallel Applications.

2014English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy