Approaching the Theoretical Limits of a Mesh NoC With a 16-Node Chip Prototype in 45nm SOI

doi 10.1145/2228360.2228431
Full Text
Abstract

Available in full text

Date
Authors
Publisher

ACM Press

Related search

A Theoretical Study of Low Power Soi Technology

IOSR Journal of VLSI and Signal Processing
2013English

A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-On-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

2014English

The Approaching Eclipse of the Sun, April 16, 1893

Nature
Multidisciplinary
1893English

A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-On-Chip Load in 45 Nm SOI

IEEE Journal of Solid-State Circuits
Electronic EngineeringElectrical
2012English

The Approaching Solar Eclipse, April 15–16, 1893

Nature
Multidisciplinary
1893English

Design of a Switching Node (Router) for On-Chip Networks

2003English

Electrical Impact of Line-Edge Roughness on Sub-45nm Node Standard Cell

2009English

Understanding the Effect of Laser Anneal on LSTP 45nm Node MOS Transistor Electrical Parameters

2008English

A Virtual Node Algorithm for Changing Mesh Topology During Simulation

2004English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy