IC Layout Design of 4-Bit Magnitude Comparator Using Electric VLSI Design System

IOSR Journal of VLSI and Signal Processing
doi 10.9790/4200-0702016773
Full Text
Abstract

Available in full text

Date
Authors
Publisher

IOSR Journals

Related search

4-Bit Multiplier Design Using CMOS Gates in Electric VLSI

International Journal of Recent Technology and Engineering
EngineeringManagement of TechnologyInnovation
2019English

Low Power Magnitude Comparator Circuit Design

International Journal of Computer Applications
2014English

CMOS VLSI Design of Low Power Comparator Logic Circuits

Asian Journal of Scientific Research
Multidisciplinary
2014English

Design of 1-Bit Comparator Using 2 Dot 1 Electron Quantum-Dot Cellular Automata

International Journal of Advanced Computer Science and Applications
Computer Science
2017English

Design of Double Tail Comparator Using Dual Mode Logic in PTL Design

International Journal of Innovative Research in Computer and Communication Engineering
2015English

Embedding Graphs in Books: A Layout Problem With Applications to VLSI Design

SIAM Journal on Algebraic Discrete Methods
1987English

Qca Design for 4-Bit Asynchronous Down Counter

International Journal of Advances in Signal and Image Sciences
2017English

Digital NBC Protection System BIT Optimization Design

MATEC Web of Conferences
Materials ScienceEngineeringChemistry
2019English

An 11-Bit Single-Ended SAR ADC With an Inverter-Based Comparator for Design Automation

IEICE Transactions on Electronics
Electronic EngineeringOpticalElectricalMagnetic MaterialsElectronic
2016English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy