Amanote Research

Amanote Research

    RegisterSign In

A CMOS Input Buffer With Linearization Technique for High-Speed a/D

doi 10.2991/ic3me-15.2015.175
Full Text
Open PDF
Abstract

Available in full text

Date

January 1, 2015

Authors
Xi ChenLiang LiMingyuan XuXiaofeng Shen
Publisher

Atlantis Press


Related search

Compact Low-Power High Slew-Rate CMOS Buffer Amplifier With Power Gating Technique

International Journal of VLSI Design & Communication Systems
2014English

Buffer Dumping Management for High Speed Routers

English

High-Speed Interruption Technique for a Vacuum Arc

IEEJ Transactions on Power and Energy
Electronic EngineeringPower TechnologyElectricalEnergy Engineering
1985English

A Module Generator for High-Speed CMOS Current Output Digital/Analog Converters

IEEE Journal of Solid-State Circuits
Electronic EngineeringElectrical
1996English

A Low Input Referred Noise Dynamic Comparator for High Speed Applications

International Journal of Recent Technology and Engineering
EngineeringManagement of TechnologyInnovation
2019English

Copper Metallization for High-Speed ECL-CMOS LSI's

1999English

A Wired-And Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC

1997English

A High-Speed CMOS Current Op Amp for Very Low Supply Voltage Operation

English

A Linearization Technique for Active Mixers in Zero-If Receivers With Inherent Balun

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2011English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy