Synthesis of Robust Delay-Fault-Testable Circuits: Theory

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - United States
doi 10.1109/43.108622
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Related search

RP-SYN: Synthesis of Random Pattern Testable Circuits With Test Point Insertion

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ElectricalSoftwareComputer GraphicsComputer-Aided DesignElectronic Engineering
1999English

Robust Analytical Gate Delay Modeling for Low Voltage Circuits

2006English

Evolutionary Synthesis of Logic Circuits Using Information Theory

Artificial Intelligence Review
LinguisticsLanguageArtificial Intelligence
2003English

Signature Analysis and Test Scheduling for Self-Testable Circuits

English

Robust Fault Detection of Linear Uncertain Time-Delay Systems Using Unknown Input Observers

Journal of Applied Mathematics
Applied Mathematics
2013English

Robust Fault Detection for Uncertain System With Communication Delay and Measurement Missing

2017English

Robust Fault Detection for Networked Systems With Communication Delay and Data Missing

Automatica
ControlSystems EngineeringElectricalElectronic Engineering
2009English

Sampled-Data Sliding Mode Observer for Robust Fault Reconstruction: A Time-Delay Approach

Journal of the Franklin Institute
ControlSystems EngineeringSignal ProcessingComputer NetworksApplied MathematicsCommunications
2014English

Electronically Controllable Delay Circuits

The Journal of the Institute of Television Engineers of Japan
1961English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy