Design of a Very Low-Power, Low-Cost 60 GHz Receiver Front-End Implemented in 65 Nm CMOS Technology

International Journal of Microwave and Wireless Technologies - United Kingdom
doi 10.1017/s1759078711000067
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Cambridge University Press (CUP)

Related search

Erratum To: Folded Down-Conversion Mixer for a 60 GHz Receiver Architecture in 65-Nm CMOS Technology

Frontiers of Information Technology and Electronic Engineering
Electronic EngineeringSignal ProcessingComputer NetworksHardwareCommunicationsElectricalArchitecture
2015English

A 65–77 GHz Low Power, Meander-Type Transmission Line CMOS Low-Noise Amplifier

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2015English

A Low-Power Fully Integrated CMOS RF Receiver for 2.4-GHz-Band IEEE 802.15.4 Standard

2015English

Design a Low Power Half-Subtractor Using .90µm CMOS Technology

IOSR journal of VLSI and Signal Processing
2013English

A Design of Receiver Front-End Low-Noise Electrical Tuning Amplifier Circuit

2015English

CLARO-CMOS: A Fast, Low Power and Radiation-Hard Front-End ASIC for Single-Photon Counting in 0.35 Micron CMOS Technology

2015English

A 2-Stage Low Noise Amplifier in 90 Nm CMOS for 2.4 GHz Applications

Advanced Science Letters
Environmental ScienceEnergyEngineeringHealthComputer ScienceMathematicsEducation
2016English

Design of Low Power SAR ADC for ECG Using 45nm CMOS Technology

International Journal of VLSI Design & Communication Systems
2017English

Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

VLSI Design
Electronic EngineeringComputer GraphicsHardwareElectricalArchitectureComputer-Aided Design
2007English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy