Amanote Research

Amanote Research

    RegisterSign In

Choice of Tests for Logic Verification and Equivalence Checking and the Use of Fault Simulation

doi 10.1109/icvd.2000.812626
Full Text
Open PDF
Abstract

Available in full text

Date

Unknown

Authors
V.D. Agrawal
Publisher

IEEE Comput. Soc


Related search

Verification of Concurrent Quantum Protocols by Equivalence Checking

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2014English

Verification of Source Code Transformations by Program Equivalence Checking

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2005English

Exact Logic and Fault Simulation in Presence of Unknowns

ACM Transactions on Design Automation of Electronic Systems
Computer Science ApplicationsElectronic EngineeringComputer GraphicsElectricalComputer-Aided Design
2014English

On the Use of Probabilistic Model-Checking for the Verification of Prognostics Applications

2015English

On Verification of Superiority in Pharmacometrics and the Equivalence Verification.

Japanese Journal of Clinical Pharmacology and Therapeutics
Pharmacology
1993English

A Methodology for Hardware Verification Based on Logic Simulation.

1987English

Client-Specific Equivalence Checking

2018English

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Journal of Electronic Testing: Theory and Applications (JETTA)
Electronic EngineeringElectrical
2005English

Runtime Checking for Program Verification

English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy