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Buffer Tree Synthesis With Consideration of Temporal Locality, Sink Polarity Requirements, Solution Cost, Congestion, and Blockages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- United States
doi 10.1109/tcad.2003.809648
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Categories
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
Date
April 1, 2003
Authors
M. Hrkic
J. Lillis
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
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