High-Speed Redundant Binary Adder-Subtractor Representing Each Digit by Hybrid 2 Bits/3 Bits
IEEJ Transactions on Electronics, Information and Systems - Japan
doi 10.1541/ieejeiss1987.121.4_733
Full Text
Open PDFAbstract
Available in full text
Date
January 1, 2001
Authors
Publisher
Institute of Electrical Engineers of Japan (IEE Japan)