Processor Subsystem Interconnect Architecture for a Large Symmetric Multiprocessing System

IBM Journal of Research and Development - United States
doi 10.1147/rd.483.0323
Full Text
Abstract

Available in full text

Date
Authors
Publisher

IBM

Related search

A Reconfigurable Optoelectronic Interconnect Technology for Multi-Processor Networks

English

Interconnect Enhancements for a High-Speed PLD Architecture

2002English

A Scheduling Algorithm for Asymmetric Processor Architecture

International Journal of Computer Applications
2010English

Packaging Technologies of Optical Circuits. Optical Subsystem Interconnect Technology.

The Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits
1995English

High-Speed Interconnect and Packaging Design of the IBM System Z9 Processor Cage

IBM Journal of Research and Development
Computer Science
2007English

A System-Level Design Method for Cognitive Radio on a Reconfigurable Multi-Processor Architecture

2007English

Architecture-Level Synthesis for Automatic Interconnect Pipelining

2004English

A Java Processor Architecture for Embedded Real-Time Systems

Journal of Systems Architecture
HardwareArchitectureSoftware
2008English

SAGE: An Automatic Analyzing System for a New High-Performance SoC Architecture––processor-In-Memory

Journal of Systems Architecture
HardwareArchitectureSoftware
2004English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy