Amanote Research
Register
Sign In
CORDIC Arithmetic for an SVD Processor
doi 10.1109/arith.1987.6158686
Full Text
Open PDF
Abstract
Available in
full text
Date
May 1, 1987
Authors
Joseph R. Cavallaro
Franklin T. Luk
Publisher
IEEE
Related search
The Reconfigurable Arithmetic Processor
ACM SIGARCH Computer Architecture News
A New Memory Reduced Radix-4 CORDIC Processor for FFT Operation
IOSR Journal of VLSI and Signal Processing
A CORDIC Processor for FFT Computation and Its Implementation Using Gallium Arsenide Technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Lightweight Conversion From Arithmetic to Boolean Masking for Embedded IoT Processor
Applied Sciences (Switzerland)
Instrumentation
Materials Science
Fluid Flow
Engineering
Computer Science Applications
Process Chemistry
Transfer Processes
Technology
A Fault-Tolerant Permutation Network Modulo Arithmetic Processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Optimal Synthesis of Processor Arrays With Pipelined Arithmetic Units
Parallel Processing Letters
Hardware
Theoretical Computer Science
Architecture
Software
SVD-MPE: An SVD-Based Vector Extrapolation Method of Polynomial Type
Applied Mathematics
P-Cordic: A Precomputation Based Rotation CORDIC Algorithm
Eurasip Journal on Advances in Signal Processing
Hardware
Electronic Engineering
Signal Processing
Electrical
Architecture
An SVD-based Watermarking Scheme for Protecting Rightful Ownership
IEEE Transactions on Multimedia
Electronic Engineering
Media Technology
Computer Science Applications
Electrical
Signal Processing
