Analysis of Error Recovery Schemes for Networks on Chips

IEEE Design and Test of Computers
doi 10.1109/mdt.2005.104
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Related search

Opportunities and Challenges for Error Control Schemes for Wireless Sensor Networks: A Review

Electronics (Switzerland)
ControlElectronic EngineeringSignal ProcessingComputer NetworksSystems EngineeringHardwareCommunicationsElectricalArchitecture
2020English

Grid Convergence Error Analysis for Mixed-Order Numerical Schemes

2001English

Error Analysis of Padding Schemes for DFT's of Convolutions and Derivatives

1998English

Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip

2007English

New Recovery Error Indicator for Adaptive Finite-Element Analysis on Waveguiding Structures

IEEE Transactions on Microwave Theory and Techniques
Electronic EngineeringRadiationElectricalCondensed Matter Physics
2003English

On the Performance Analysis of Different Link to Path Restoration Schemes for All-Optical Networks

2012English

Blending Interpolation Schemes on Triangles With Error Bounds

Lecture Notes in Mathematics
Number TheoryAlgebra
1977English

Educational Magic Tricks Based on Error-Detection Schemes

2017English

A Posteriori Error Estimates for Pressure-Correction Schemes

SIAM Journal on Numerical Analysis
Computational MathematicsApplied MathematicsNumerical Analysis
2016English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy