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Publications by D.R. Ditzel
CRISP: A Pipelined 32-Bit Microprocessor With 13-Kbit of Cache Memory
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
Related publications
A 20-Mips Sustained 32-Bit CMOS Microprocessor With High Ratio of Sustained to Peak Performance
IEEE Journal of Solid-State Circuits
Electronic Engineering
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Novel Design of 32-Bit Asynchronous (RISC) Microprocessor & Its Implementation on FPGA
International Journal of Information Engineering and Electronic Business
Implementation of 5-Stage 32-Bit Microprocessor Based Without Interlocked Pipelining Stages
International Journal of Innovative Technology and Exploring Engineering
Mechanics of Materials
Electronic Engineering
Civil
Structural Engineering
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Computer Science
A Dynamic Scratchpad Memory Collaborated With Cache Memory for Transferring Data for Multi-Bit Error Correction
International Journal of Trend in Scientific Research and Development
Information Technology. Microprocessor Systems. High-Performance Synchronous 32-Bit Bus: MULTIBUS II
Design and Implementation of Synthesizable 32-Bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL
Nepal Journal of Science and Technology
Design of Cache Memory With Cache Controller for Low Power
32-Bit MIPS RISC Processor
International Journal for Research in Applied Science and Engineering Technology
Reducing Cache Power With Low-Cost, Multi-Bit Error-Correcting Codes
ACM SIGARCH Computer Architecture News
