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Publications by G. R. Dharmasena
Development of Sensitivity and Offset Calibratable Capacitance Detection CMOS IC Using PLL Configuration
IEEJ Transactions on Sensors and Micromachines
Electronic Engineering
Electrical
Mechanical Engineering
Related publications
Low-Power Design of Adiabatic Dynamic CMOS Logic Using Parasitic Capacitance of 0.18μm Standard CMOS Model
CMOS Op-Amp Offset Calibration Technique Using a Closed Loop Offset Amplifier and Compact Resistor String DAC
Radon Detection Using CMOS Alpha Sensor
The Impact of Noise and Mismatch on SAR ADCs and a Calibratable Capacitance Array Based Approach for High Resolutions
International Journal of Electronics and Telecommunications
Low Power Current Mode ADC for CMOS Sensor IC
Four-Plate Pick-Up Capacitance and Sensitivity Calculations
Optimizing the Configuration of Development Teams Using EVA
International Journal of Information Technology Project Management
Information Systems
Organizational Behavior
Communication
Management Information Systems
Strategy
Management
Innovation
Management of Technology
Human Resource Management
IC Defect Sensitivity for Footprint-Type Spot Defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
Optimization of STI Stress and Active Geometry Configuration for Advanced CMOS Devices
