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Publications by Ishan Sachdev
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
ACM SIGARCH Computer Architecture News
Related publications
Aegis: A Single-Chip Secure Processor
IEEE Design & Test of Computers
Design and Implementation of Floating Point FFT Processor Using VHDL
IOSR Journal of VLSI and Signal Processing
Physical Unclonable Functions and Secure Processors
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
Design and Implementation of the Delft Molecular-Dynamics Processor
System-On-Chip Design and Implementation
IEEE Transactions on Education
Electronic Engineering
Education
Electrical
Design and Implementation of a Network on Chip Using FPGA(English)
AL-Rafdain Engineering Journal (AREJ)
ANALYSIS AND DESIGN OF a MODIFIED GO-CFAR PROCESSOR. HARDWARE IMPLEMENTATION USING PLDs.
The International Conference on Electrical Engineering
Processor Design Using 32 Bit Single Precision Floating Point Unit
International Journal of Trend in Scientific Research and Development
Design and Implementation of Secure Stream Cipher Algorithm
International Journal of Computing and Digital Systems
Computer Graphics
Human-Computer Interaction
Computer Networks
Communications
Information Systems
Computer-Aided Design
Innovation
Management of Technology
Artificial Intelligence
