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Publications by J. Dhurga Devi

Jitter Reduced Self Biased PLLs—A Systematic Simulation Study

Circuits and Systems

English

Related publications

A Low Jitter Phase-Locked Loop Based on Self-Biased Techniques

IEICE Electronics Express

Electronic Engineering

Condensed Matter Physics

Magnetic Materials

English

Wavelet-Based Signal Design for Reduced Jitter Timing-Recovery

IEEE Transactions on Communications

Electronic Engineering

English

A Self-Learning Algorithm for Biased Molecular Dynamics

Proceedings of the National Academy of Sciences of the United States of America

Multidisciplinary

English

Reduced-Bias Location-Invariant Extreme Value Index Estimation: A Simulation Study

Communications in Statistics Part B: Simulation and Computation

English

A Simulation Study on Defectivity in Directed Self-Assembly Lithography

Journal of Photopolymer Science and Technology

Organic Chemistry

Materials Chemistry

English

Dual-Phase Self-Biased Magnetoelectric Energy Harvester

Applied Physics Letters

English

A Study of the Electrical Properties of Self-Biased Channel MOS Diodes for Solar-Cell Applications

Journal of International Council on Electrical Engineering

English

A Calibration Scheme for Stability of Self-Biased Ring Amplifier

English

Ensemble-Biased Metadynamics: A Molecular Simulation Method to Sample Experimental Distributions

Biophysical Journal

English