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Publications by Kenji Kogo

Design Procedure of 25.8 GBPS/Lane Re-Timer IC Regarding Power Integrity

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2017English

Related publications

Operational Manual and Acceptance Test Procedure for WANL ETS-1 Power Increase Timer Model 937J845G01

1966English

Design and Analysis of Low Power Level Shifter in IC Applications

International Journal of Computer Applications
2016English

Efficient Power/Ground Network Analysis for Power Integrity-Driven Design Methodology

2004English

Design of Transcutaneous Electrical Nerve Stimulating Machine Using 555 Timer and 7555 Timer

International Journal of Science and Research (IJSR)
2016English

Design on ESD Protection Scheme for IC With Power-Down-Mode Operation

IEEE Journal of Solid-State Circuits
Electronic EngineeringElectrical
2004English

Design of Watchdog Timer for Real Time Applications

International Journal of Innovative Technology and Exploring Engineering
Mechanics of MaterialsElectronic EngineeringCivilStructural EngineeringElectricalComputer Science
2019English

Lane-Level Map-Matching With Integrity on High-Definition Maps

2017English

Design and Implementation of Astable Multivibrator Using 555 Timer

IOSR Journal of Electrical and Electronics Engineering
2017English

Overview of Radiation Hardening Techniques for IC Design

Information Technology Journal
2010English

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