Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by R.G. Burford
An 180 MHz 16 Bit Multiplier Using Asynchronous Logic Design Techniques
Related publications
Energy-Efficient Approximate Multiplier Design Using Bit Significance-Driven Logic Compression
4-Bit Multiplier Design Using CMOS Gates in Electric VLSI
International Journal of Recent Technology and Engineering
Engineering
Management of Technology
Innovation
20 GHz Operation of Bit-Serial Handshaking Systems Using Asynchronous SFQ Logic Circuits
IEEE Transactions on Applied Superconductivity
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Design of Pulse Detectors and Unsigned Sequential Multiplier Using Reversible Logic
International Journal of Computer Applications
Qca Design for 4-Bit Asynchronous Down Counter
International Journal of Advances in Signal and Image Sciences
Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics With Bit Reduction Technique
Circuits and Systems
A New Design of Multiplier Using Modified Booth Algorithm and Reversible Gate Logic
International Journal of Computer Applications Technology and Research
Design of Low Power SRAM Using Hierarchical Divided Bit-Line Approach in 180-Nm Technology
International Journal of Engineering Research and
A 16-Bit High-Speed Multiplier Design Based on Karatsuba Algorithm and Urdhva-Tiryagbhyam Theorem Using Modified Gdi Cells for Low Power and Area Constraints
ICTACT Journal on Microelectronics