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Publications by Raju Yanamshetti
Design of Nova Decoder for H.265/Hevc
International Journal of Computer Applications
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Intra Prediction Header Bits Estimation Algorithm for RDO in H.265/Hevc
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A Cost – Effective Programmable SoC for H.265/Hevc Full Search Motion Estimation Using Xilinx ZYNQ-7 ZC706 FPG
International Journal of Computing and Network Technology
A Low-Cost Complexity Intra Prediction Hardware Architecture for HEVC Decoder
International Journal of Recent Technology and Engineering
Engineering
Management of Technology
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Design of High-Performance Intra Prediction Circuit for H.264 Video Decoder
Journal of Semiconductor Technology and Science
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H.264 Decoder Design Using Verilog (With Simulation Results)
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A 249-Mpixel/S HEVC Video-Decoder Chip for 4K Ultra-Hd Applications
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Uporedna Analiza Standarda H.264 I H.265
Zbornik radova Fakulteta tehničkih nauka u Novom Sadu
A Generalized Hypothetical Reference Decoder for H.264/Avc
IEEE Transactions on Circuits and Systems for Video Technology
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