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Publications by S. Rajopadhye
Combined Instruction and Loop Parallelism in Array Synthesis for FPGAs
A Sparse Knapsack Algo-Tech-Cuit and Its Synthesis
Related publications
Multilevel Granularity Parallelism Synthesis on FPGAs
Loop-Level Parallelism in Numeric and Symbolic Programs
IEEE Transactions on Parallel and Distributed Systems
Hardware
Computational Theory
Signal Processing
Architecture
Mathematics
Synthesis Optimization for Finite State Machine Design in FPGAs
International Journal of VLSI Design & Communication Systems
Loop Optimization for Aggregate Array Computations
Design and Analysis of Efficient Synthesis Algorithms for EDAC Functions in FPGAs
IEEE Transactions on Aerospace and Electronic Systems
Electronic Engineering
Electrical
Aerospace Engineering
The Power of Parallelism for Automatic Program Synthesis
A Review on Superscalar Technology With Instruction Level Parallelism (ILP) for Faster Microprocessor
International Journal for Research in Applied Science and Engineering Technology
Combined Two Frequency Array for Optoacoustics and Acoustics
Journal of the Acoustical Society of America
Acoustics
Ultrasonics
Arts
Humanities
From Software Threads to Parallel Hardware in High-Level Synthesis for FPGAs
