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Publications by V. S. Jayanthi

Low Power Adder Based Auditory Filter Architecture

The Scientific World Journal

Molecular Biology

Environmental Science

English

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Low Power Adder Based ANN

International Journal of Computer Applications

English

Low Power Wallace and Dadda Multiplier Based on CLRCL Full Adder

English

Low Power Circuit for Brent-Kung Adder Based on Adiabatic Logic

International Journal of Advances in Signal and Image Sciences

English

Low Power High Speed SQRT Carry Select Adder

IOSR journal of VLSI and Signal Processing

English

A Novel Low Power Adder-Subtractor Using Efficient XOR Gates

Journal of Applied Sciences

English

Design and Analysis of Multi Vt and Variable Vt Based Pipelined Adder for Low Power Applications

International Journal of VLSI Design & Communication Systems

English

A Time Driven Adder Generator Architecture

English

Trade-Offs in Designing High-Performance Digital Adder Based on Heterogeneous Architecture

International Journal of Computer Applications

English

Testing Ripple Carry Adder Using Bist Architecture

International Journal of Engineering and Technology(UAE)

Chemical Engineering

Environmental Engineering

Computer Science

English