Amanote Research
Register
Sign In
High Speed Low Complexity Radix-16 Max-Log-Map SISO Decoder
doi 10.1109/icecs.2012.6463718
Full Text
Open PDF
Abstract
Available in
full text
Date
December 1, 2012
Authors
Oscar Sanchez
Christophe Jegoy
Michel Jezequel
Yannick Saouter
Publisher
IEEE
Related search
Reduced-Complexity Approx-Log-Map and Max-Log-Map Soft PSK/QAM Detection Algorithms
IEEE Transactions on Communications
Electronic Engineering
Electrical
Fpga Implementation of Polar Codes for Low Complexity Decoder for High Speed Applications
International Journal of Innovative Technology and Exploring Engineering
Mechanics of Materials
Electronic Engineering
Civil
Structural Engineering
Electrical
Computer Science
Design and Comparison of High Speed Radix-8 and Radix-16 Booth’s Multipliers
International Journal of Computer Applications
High Speed Low-Power Viterbi Decoder Using Trellis Code Modulation
International Journal of Computing Algorithm
Low Complexity Decoder for CCSDS Turbo Codes
IOSR Journal of Electronics and Communication Engineering
Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder
IFIP Advances in Information and Communication Technology
Computer Networks
Information Systems
Management
Communications
Low-Complexity Shift Register Based on Decoder Enabled Pulsed Latches
The International Journal of Engineering and Science
A Low-Cost Complexity Intra Prediction Hardware Architecture for HEVC Decoder
International Journal of Recent Technology and Engineering
Engineering
Management of Technology
Innovation
A Low Complexity PAPR Reduction Scheme Based on Radix-Ii IFFT
