Low Power and High Speed 13T SRAM Cell With Bit-Interleaving Capability

International Journal of Computer Applications
doi 10.5120/ijca2016909859
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Foundation of Computer Science

Related search

Power and Area Efficient Sub-Threshold 6T SRAM With Horizontal Local Bit-Lines and Bit-Interleaving

English

Comparison of the Interconnect Capacitances of Various SRAM Cell Layouts to Achieve High Speed, Low Power SRAM Cells

2003English

Comparative Analysis of Various SRAM Cells With Low Power, High Read Stability and Low Area

International Journal of Engineering and Manufacturing
2014English

Design and Analysis of Two Low-Power SRAM Cell Structures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HardwareElectronic EngineeringElectricalArchitectureSoftware
2009English

Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants

International Journal of Computer Applications
2015English

Design of Low Power SRAM Using Hierarchical Divided Bit-Line Approach in 180-Nm Technology

International Journal of Engineering Research and
2016English

7T Based SRAM Topologies With Low Power and Higher SNM

International Journal of Innovative Technology and Exploring Engineering
Mechanics of MaterialsElectronic EngineeringCivilStructural EngineeringElectricalComputer Science
2019English

A Review on Low Power Sram

International Journal of Recent Trends in Engineering and Research
2017English

Low Power High Speed SQRT Carry Select Adder

IOSR journal of VLSI and Signal Processing
2012English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy