Amanote Research
Register
Sign In
A 231-MHz, 2.18-mW 32-Bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System
IEEE Journal of Solid-State Circuits
- United States
doi 10.1109/jssc.2006.882887
Full Text
Open PDF
Abstract
Available in
full text
Categories
Electronic Engineering
Electrical
Date
November 1, 2006
Authors
H. Kim
B.-G. Nam
J.-H. Sohn
J.-H. Woo
H.-J. Yoo
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Related search
Design of FPGA Based 32-Bit Floating Point Arithmetic Unit and Verification of Its VHDL Code Using MATLAB
International Journal of Information Engineering and Electronic Business
Processor Design Using 32 Bit Single Precision Floating Point Unit
International Journal of Trend in Scientific Research and Development
Logarithmic Arithmetic as an Alternative to Floating-Point: A Review
A Monte-Carlo Floating-Point Unit for Self-Validating Arithmetic
Some Fixed Point Theorems in Logarithmic Convex Structures
A 32-mW 320-MHz Continuous-Time Complex Delta-Sigma ADC for Multi-Mode Wireless-Lan Receivers
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
The DIII-D 3 MW, 110 GHz ECH System
Design and Implementation 4-Bit Quaternary MVL Arithmetic and Logic Unit
Tehnicki Vjesnik
Engineering
3-D Graphics Animation Program for the Apple II
Behavior Research Methods, Instruments, & Computers
