Amanote Research

Amanote Research

    RegisterSign In

Designing Best Effort Networks-On-Chip to Meet Hard Latency Constraints

Transactions on Embedded Computing Systems - United States
doi 10.1145/2485984.2485996
Full Text
Open PDF
Abstract

Available in full text

Categories
HardwareArchitectureSoftware
Date

June 1, 2013

Authors
Ciprian SeiculescuDara RahmatiSrinivasan MuraliHamid Sarbazi-AzadLuca BeniniGiovanni De Micheli
Publisher

Association for Computing Machinery (ACM)


Related search

Best-Effort Authentication for Opportunistic Networks

2011English

A Low Latency Wormhole Router for Asynchronous On-Chip Networks

2010English

Throughput Anonymity Trade-Off in Wireless Networks Under Latency Constraints

2008English

On Finite-Horizon Control of Genetic Regulatory Networks With Multiple Hard-Constraints

BMC Systems Biology
Molecular BiologyApplied MathematicsStructural BiologySimulationComputer Science ApplicationsModeling
2010English

Constraints Meet Concurrency

Atlantis Studies in Computing
2014English

Performance of Nonlinear Queue Management Algorithms in Best-Effort Networks

IFAC Proceedings Volumes
2005English

Imposing Hard Constraints on Soft Snakes

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
1996English

Capacity Planning of DiffServ Networks With Best-Effort and Expedited Forwarding Traffic

English

Supporting Scalable Analytics With Latency Constraints

Proceedings of the VLDB Endowment
Computer Science
2015English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy