FPGA Implementation of RS Codec With Interleaver in DVB-T Using VHDL

International Journal of Engineering and Technology(UAE) - United Arab Emirates
doi 10.14419/ijet.v6i4.8205
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Science Publishing Corporation

Related search

VHDL Implementation of AES-128 on FPGA

IJIREEICE
2015English

Digital Design and Simulation of CVSD Codec Algorithm Using VHDL

International Journal of Research in Engineering and Technology
2017English

Design and Implementation of Synthesizable 32-Bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL

Nepal Journal of Science and Technology
2015English

Design and Implementation of RS (255, 223) Detecting Code in FPGA

International Journal of Computer Applications
2015English

Study of Timing Synchronization in MIMOOFDM Systems Using DVB-T

International Journal on Information Theory
2014English

Implementation of RS Encoder and RS Decoder Using UHD Architecture

International Journal of Computer Applications
2013English

Design and Implementation of Floating Point FFT Processor Using VHDL

IOSR Journal of VLSI and Signal Processing
2013English

VHDL Implementation of Nor Flash Controller

International Journal of Electronics and Communication Engineering
2017English

VHDL Implementation of GCD Processor With Built in Self Test Feature

International Journal of Computer Applications
2011English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy