Amanote Research

Amanote Research

    RegisterSign In

Line-Rate Packet Processing in Hardware: The Evolution Towards 400 Gbit/S

doi 10.14794/icai.9.2014.1.259
Full Text
Open PDF
Abstract

Available in full text

Date

January 1, 2015

Authors
Tamás TóthfalusiPéter Orosz
Publisher

Eszterházy Károly College


Related search

The P4->NetFPGA Workflow for Line-Rate Packet Processing

2019English

Optical Packet Transmission in 42.6 Gbit/S Wavelength-Division-Multiplexed Clockwork-Routed Networks

Journal of Optical Networking
2008English

Programmable Packet Scheduling at Line Rate

2016English

Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware

English

Towards Formal Verification of TLS Network Packet Processing Written in C

2013English

100-Gbit/S Full-Rate Operation of PD-EAM Optical Gate for Retiming Function

2003English

Towards Signal Processing Assisted Hardware for Continuous In-Band Electrode Impedance Monitoring (Invited Paper)

2017English

Experimental Demonstration of Packet-Rate 10-Gb/S OOK OSNR Monitoring for QoS-aware Cross-Layer Packet Protection

Optics Express
OpticsAtomicMolecular Physics,
2011English

Gbit/S Ultraviolet-C Diffuse-Line-Of-Sight Communication Based on Probabilistically Shaped DMT and Diversity Reception

Optics Express
OpticsAtomicMolecular Physics,
2020English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy