Amanote Research
Register
Sign In
Corrigendum to “An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization”
International Journal of Reconfigurable Computing
- United States
doi 10.1155/2018/6075043
Full Text
Open PDF
Abstract
Available in
full text
Categories
Hardware
Architecture
Date
June 21, 2018
Authors
O. Ahmed
S. Areibi
R. Collier
G. Grewal
Publisher
Hindawi Limited
Related search
An FPGA-based Hardware Accelerator for Iris Segmentation
On-Chip Hardware Accelerator for DSP Applications
International Journal of Recent Technology and Engineering
Engineering
Management of Technology
Innovation
Macro to Micro Learning Design: From Coarse/Course to Fine Grain Student Interactions
Journal of Learning Design
An Automated Surveillance System Based on Multi-Processor System-On-Chip and Hardware Accelerator
International Journal of Advanced Computer Science and Applications
Computer Science
pvFPGA: Paravirtualising an FPGA-based Hardware Accelerator Towards General Purpose Computing
International Journal of High Performance Computing and Networking
Hardware
Computer Networks
Software
Architecture
Communications
An Adaptive Cache Replacement Policy Based on Fine-Grain Reusability Monitor
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Hardware Accelerator Design for Data Centers
An Atlas-Based Deep Brain Structure Segmentation Method: From Coarse Positioning to Fine Shaping
Open Hardware for CERN's Accelerator Control Systems
Journal of Instrumentation
Instrumentation
Mathematical Physics