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Formal Automatic Verification of Cache Coherence in Multiprocessors With Relaxed Memory Models
IEEE Transactions on Parallel and Distributed Systems
- United States
doi 10.1109/71.879780
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Categories
Hardware
Computational Theory
Signal Processing
Architecture
Mathematics
Date
January 1, 2000
Authors
M. Dubois
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
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