Memory Contention in Scalable Cache-Coherent Multiprocessors

doi 10.21236/ada272946

Full Text

Abstract

Available in

Date

April 1, 1993

Authors

Ricardo Bianchini

Mark E. Crovella

Leonidas Kontothanassiss

Thomas J. LeBlanc

Publisher

Defense Technical Information Center

Related search

An Efficient Cache Design for Scalable Glueless Shared-Memory Multiprocessors

English

Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors

ACM SIGARCH Computer Architecture News

English

Cache Coherence Protocols in Shared-Memory Multiprocessors

English

An Advanced Compiler Framework for Non-Cache-Coherent Multiprocessors

IEEE Transactions on Parallel and Distributed Systems

Computational Theory

Signal Processing

English

Quantifying Contention and Balancing Memory Load on Hardware DSM Multiprocessors

Journal of Parallel and Distributed Computing

Computer Networks

Theoretical Computer Science

Artificial Intelligence

English

Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors

English

Formal Automatic Verification of Cache Coherence in Multiprocessors With Relaxed Memory Models

IEEE Transactions on Parallel and Distributed Systems

Computational Theory

Signal Processing

English

Cache-Hierarchy Contention-Aware Scheduling in CMPs

IEEE Transactions on Parallel and Distributed Systems

Computational Theory

Signal Processing

English

Optimizing Shared Cache Behavior of Chip Multiprocessors

English