Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

IEEE Transactions on Industrial Informatics - United States
doi 10.1109/tii.2012.2235844
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Related search

Particle Swarm Optimization for HW/SW Partitioning

2009English

HW/SW Partitioning and Code Generation of Embedded Control Applications on a Reconfigurable Architecture Platform

2002English

An FPGA Implementation of HW/SW Codesign Architecture for H.263 Video Coding

2011English

Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design

English

Fragmentation Management for HW Multitasking in 2D Reconfigurable Devices: Metrics and Defragmentation Heuristics

2010English

Collective Behavior Bees for Solving HW/SW Partitioning and Scheduling Problems in RSoC

Transactions on Machine Learning and Artificial Intelligence
2017English

Development of the Reconfiguration Acceleration Method in the Dynamically Reconfigurable Computing Systems

EasternEuropean Journal of Enterprise Technologies
ControlElectronic EngineeringIndustrialMechanical EngineeringEnergy EngineeringApplied MathematicsSystems EngineeringManufacturing EngineeringComputer Science ApplicationsElectricalInnovationManagement of TechnologyPower Technology
2015English

An FPGA-Based HOG Accelerator With HW/SW Co-Design for Human Detection and Its Application to Crowd Density Estimation

Journal of Software Engineering and Applications
2019English

RTDT: A Static QoS Manager, RT Scheduling, HW/SW Partitioning CAD Tool

Microelectronics Journal
2006English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy