Amanote Research

Amanote Research

    RegisterSign In

Speculative Execution for Hiding Memory Latency

ACM SIGARCH Computer Architecture News
doi 10.1145/1101868.1101877
Full Text
Open PDF
Abstract

Available in full text

Date

June 1, 2005

Authors
Alex PajueloAntonio GonzálezMateo Valero
Publisher

Association for Computing Machinery (ACM)


Related search

Speculative Execution Plan for Multiple Query Execution Systems

Annales UMCS, Informatica
2010English

Coarse-Grained Thread Pipelining: A Speculative Parallel Execution Model for Shared-Memory Multiprocessors

IEEE Transactions on Parallel and Distributed Systems
HardwareComputational TheorySignal ProcessingArchitectureMathematics
2001English

Dynamically Dispatching Speculative Threads to Improve Sequential Execution

Transactions on Architecture and Code Optimization
HardwareInformation SystemsArchitectureSoftware
2012English

Using Speculative Execution for Fault Tolerance in a Real-Time System

English

SEED: A Statically Greedy and Dynamically Adaptive Approach for Speculative Loop Execution

IEEE Transactions on Computers
HardwareArchitectureMathematicsComputational TheoryTheoretical Computer ScienceSoftware
2013English

On the Parallelisation of McMc by Speculative Chain Execution

2010English

TMbarrier: Speculative Barriers Using Hardware Transactional Memory

2018English

The Latency Hiding Effectiveness of Decoupled Access/Execute Processors

English

Communication Latency Hiding in Reconfigurable Message-Passing Environments: Quantitative Studies

English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy