Amanote Research
Register
Sign In
Exploiting Soft Redundancy for Error-Resilient On-Chip Memory Design
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
- United States
doi 10.1109/iccad.2006.320170
Full Text
Open PDF
Abstract
Available in
full text
Categories
Computer Science Applications
Computer Graphics
Computer-Aided Design
Software
Date
November 1, 2006
Authors
Shuo Wang
Lei Wang
Publisher
IEEE
Related search
Exploiting Soft Redundancy for Error-Resilient On-Chip Memory Design
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Computer Science Applications
Computer Graphics
Computer-Aided Design
Software
Exploiting Existing Copies in Register File for Soft Error Correction
IEEE Computer Architecture Letters
Hardware
Architecture
Timing-Error-Tolerant Network-On-Chip Design Methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
Design of On-Chip Testing Memory for High Speed Circuits
CVR Journal of Science & Technology
Error-Resilient Video Transmission Using Long-Term Memory Motion-Compensated Prediction
IEEE Journal on Selected Areas in Communications
Computer Networks
Electronic Engineering
Electrical
Communications
Improving Memory After Interruption: Exploiting Soft Constraints and Manipulating Information Access Cost.
Journal of Experimental Psychology: Applied
Experimental
Cognitive Psychology
Resilient Design
International Journal of Architectural Computing
Building
Computer Graphics
Computer Science Applications
Construction
Computer-Aided Design
Insights on Error-Resilient Image Transmission Schemes on Wireless Network
International Journal of Advanced Computer Science and Applications
Computer Science
Error-Resilient Scalable Compression Based on Distributed Video Coding
Signal Processing: Image Communication
Electronic Engineering
Signal Processing
Computer Vision
Electrical
Pattern Recognition
Software