Amanote Research
Register
Sign In
Implementation of Reduced Area and Delay Integer DCT Using Modified Transposition Buffer
International Journal of Engineering Research and
doi 10.17577/ijertv4is030882
Full Text
Open PDF
Abstract
Available in
full text
Date
March 27, 2015
Authors
Unknown
Publisher
ESRSA Publications Pvt. Ltd.
Related search
Buffer-Aided Relay Selection With Reduced Packet Delay in Cooperative Networks
IEEE Transactions on Vehicular Technology
Electronic Engineering
Automotive Engineering
Computer Networks
Applied Mathematics
Communications
Electrical
Aerospace Engineering
FPGA Implementation of Low Complexity Video Encoder Using Optimized 3d-DCT
International Journal of Engineering Research and
Computation of 2D $8\times 8$ DCT Based on the Loeffler Factorization Using Algebraic Integer Encoding
IEEE Transactions on Computers
Hardware
Architecture
Mathematics
Computational Theory
Theoretical Computer Science
Software
Implementation of Invisible Digital Watermarking Technique for Copyright Protection Using DWT-SVD and DCT
International Journal of Advanced Engineering Research and Science
Implementation of Reduced Memory Viterbi Decoder Using Verilog HDL
IOSR Journal of Electronics and Communication Engineering
Fast DCT-I, DCT-III, and DCT-IV via Moments
Eurasip Journal on Advances in Signal Processing
Hardware
Electronic Engineering
Signal Processing
Electrical
Architecture
Base Station Sleeping Mechanism for Reduced Delay Using Traffic Load Prediction
VLSI Implementation of a Fairness ATM Buffer System
Transposition Pattern of a Modified Ds Element in Tomato
Plant Molecular Biology
Medicine
Genetics
Agronomy
Plant Science
Crop Science
