Automatic Layout of Domain-Specific Reconfigurable Subsystems for System-On-A-Chip

doi 10.1145/503070.503073
Full Text
Abstract

Available in full text

Date
Authors
Publisher

ACM Press

Related search

Automating the Layout of Reconfigurable Subsystems via Template Reduction

English

System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors

2006English

Chinese Automatic Question Answering System of Specific-Domain Based on Vector Space Model

IEEJ Transactions on Electronics, Information and Systems
Electronic EngineeringElectrical
2005English

Reconfigurable On-Chip Communication Link for Efficient Communication

International Journal of Engineering and Technology(UAE)
ArchitectureHardwareEngineeringChemical EngineeringBiotechnologyEnvironmental EngineeringComputer Science
2018English

Automatic Summarization of Domain-Specific Forum Threads

2017English

Reconfigurable Computing in Space: From Current Technology to Reconfigurable Systems-On-A-Chip

English

Layout Optimization Methodology for Ring-Based On-Chip Optical Network

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2019English

An Evaluation of an Integrated on-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

International Journal of Reconfigurable Computing
HardwareArchitecture
2012English

Automatic Constraint Detection for 2D Layout Regularization

IEEE Transactions on Visualization and Computer Graphics
Computer GraphicsPattern RecognitionComputer VisionComputer-Aided DesignSignal ProcessingSoftware
2016English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy