CUDA-NP: Realizing Nested Thread-Level Parallelism in GPGPU Applications

Journal of Computer Science and Technology - United States
doi 10.1007/s11390-015-1500-y
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Springer Science and Business Media LLC

Related search

Exploiting Speculative Thread-Level Parallelism in Data Compression Applications

English

An Explicit Parallelism Study Based on Thread-Level Speculation

CLEI Electronic Journal
2014English

Programming Matrix Algorithms-By-Blocks for Thread-Level Parallelism

ACM Transactions on Mathematical Software
Applied MathematicsSoftware
2009English

Data-Only Flattening for Nested Data Parallelism

ACM SIGPLAN Notices
Computer Science
2013English

Parallelism of Different Levels in the Program of Molecular Dynamics Simulation PUMA-CUDA

2018English

An Application Based Efficient Thread Level Parallelism Scheme on Heterogeneous Multicore Embedded System for Real Time Image Processing.

Scalable Computing
Computer Science
2020English

Are Web Applications Ready for Parallelism?

2017English

Are Web Applications Ready for Parallelism?

2015English

GPGPU-MiniBench: Accelerating GPGPU Micro-Architecture Simulation

IEEE Transactions on Computers
HardwareArchitectureMathematicsComputational TheoryTheoretical Computer ScienceSoftware
2015English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy