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Publications by Ashok Kumar Palaniswamy
ATPG for Delay Defects in Current Mode Threshold Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
Related publications
Dynamic Current Mode Logic Realization of Digital Arithmetic Circuits
International Journal of Computer Applications
Current and Delay Estimation in Deep Sub-Micrometer CMOS Logic Circuits
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG
Journal of Electronic Testing: Theory and Applications (JETTA)
Electronic Engineering
Electrical
Low Power Current-Mode Threshold Logic Gate Using Nano-Technology Double-Gate MOSFETs
The International Conference on Electrical Engineering
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Electronic Engineering
Computer Graphics
Signal Processing
Applied Mathematics
Electrical
Computer-Aided Design
The Use of Model Checking in ATPG for Sequential Circuits
Design and Implementation of Multi-GHz Energy-Efficient Asynchronous Pipelined Circuits in MOS Current-Mode Logic
Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
Adaptable MOS Current Mode Logic for Multi-Band Frequency Synthesizers
