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Publications by Bhavya Daya
Approaching the Theoretical Limits of a Mesh NoC With a 16-Node Chip Prototype in 45nm SOI
Related publications
A Theoretical Study of Low Power Soi Technology
IOSR Journal of VLSI and Signal Processing
A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-On-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)
The Approaching Eclipse of the Sun, April 16, 1893
Nature
Multidisciplinary
A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-On-Chip Load in 45 Nm SOI
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
The Approaching Solar Eclipse, April 15–16, 1893
Nature
Multidisciplinary
Design of a Switching Node (Router) for On-Chip Networks
Electrical Impact of Line-Edge Roughness on Sub-45nm Node Standard Cell
Understanding the Effect of Laser Anneal on LSTP 45nm Node MOS Transistor Electrical Parameters
A Virtual Node Algorithm for Changing Mesh Topology During Simulation
