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Publications by Ishika Sharma
Delay Analysis of Half Subtractor Using CMOS and Pass Transistor Logic
International Journal of Computer Applications
Related publications
CMOS-based Carbon Nanotube Pass-Transistor Logic Integrated Circuits
Nature Communications
Astronomy
Genetics
Molecular Biology
Biochemistry
Chemistry
Physics
A Novel Design of SET-CMOS Half Subtractor and Full Subtractor
International Journal of Computer Applications
Design a Low Power Half-Subtractor Using .90µm CMOS Technology
IOSR journal of VLSI and Signal Processing
High-Performance Multiplexer-Based Logic Synthesis Using Pass-Transistor Logic
VLSI Design
Electronic Engineering
Computer Graphics
Hardware
Electrical
Architecture
Computer-Aided Design
Subthreshold CMOS Logic Design Using Parallel Transistor Stacks
Minimizing Power Consumption in CMOS Full Subtractor Using SVL Technique
International Journal of Computer Applications
Transistor Sizing of Logic Gates to Maximize Input Delay Variability
Journal of Low Power Electronics
Electronic Engineering
Electrical
Designing Faster CMOS Subthreshold Circuits Using Transistor Sizing and Paralled Transistor Stacks
a High-Q Second-Order All-Pass Delay Network in CMOS
IET Circuits, Devices and Systems
Control
Systems Engineering
Electrical
Electronic Engineering
