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Publications by J. Sudha Rani
Design of Low Power Column Bypass Multiplier Using FPGA
IOSR journal of VLSI and Signal Processing
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FPGA Implementation of Low Power Digital QPSK Modulator Using Verilog HDL
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Low-Power FSMs in FPGA: Encoding Alternatives
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Experience Using a Low-Cost FPGA Design to Crack DES Keys
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FSM Decomposition for Low Power in FPGA
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Design of Booth Multiplier Using Double Gate MOSFET
International Journal of Computer Applications
