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Publications by Joseph Avey

An FPGA-based Hardware Accelerator for Iris Segmentation

English

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pvFPGA: Paravirtualising an FPGA-based Hardware Accelerator Towards General Purpose Computing

International Journal of High Performance Computing and Networking
HardwareComputer NetworksSoftwareArchitectureCommunications
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FPGA Overlays Hardware Based Computing for the Masses

2018English

Optimizing FPGA-based CNN Accelerator for Energy Efficiency With an Extended Roofline Model

Turkish Journal of Electrical Engineering and Computer Sciences
Electronic EngineeringElectricalComputer Science
2018English

Quality-Based Iris Segmentation-Level Fusion

EURASIP Journal on Information Security
2016English

Design of FPGA Hardware Based on Genetic Algorithm

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Hardware Accelerator Design for Data Centers

2015English

Architecture of an FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL

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Iris Segmentation Based on Ellipse Detection for Gaze Tracking System

2017English

An Estimating Floor Region Algorithm Based on Image Segmentation Using Fpga for Smart Rovers

2019English

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