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Publications by K. Gopi
Area Efficient Full Subtractor Based on Static 125nm CMOS Technology
International Journal of Trend in Scientific Research and Development
Related publications
A Novel Design of SET-CMOS Half Subtractor and Full Subtractor
International Journal of Computer Applications
Minimizing Power Consumption in CMOS Full Subtractor Using SVL Technique
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Design a Low Power Half-Subtractor Using .90µm CMOS Technology
IOSR journal of VLSI and Signal Processing
Area Efficient SR Flip-Flop Designed Using 90nm CMOS Technology
International Journal of Advanced Technology and Engineering Exploration
Optimized CMOS Design of Full Adder Using 45nm Technology
International Journal of Computer Applications
A Low-Voltage and Energy-Efficient Full Adder Cell Based on Carbon Nanotube Technology
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A High-Efficient Low-Voltage Rectifier for CMOS Technology
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Delay Analysis of Half Subtractor Using CMOS and Pass Transistor Logic
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Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology
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