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Publications by Keewon Cho
Efficient Systolic-Array Redundancy Architecture for Offline/Online Repair
Electronics (Switzerland)
Control
Electronic Engineering
Signal Processing
Computer Networks
Systems Engineering
Hardware
Communications
Electrical
Architecture
Related publications
A Systolic Array Architecture for the Discrete Sine Transform
IEEE Transactions on Signal Processing
Electronic Engineering
Signal Processing
Electrical
Efficient Linear Systolic Array for the Knapsack Problem
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
A Reconfigurable Systolic Array Architecture for Multicarrier Wireless Applications
High Performance Systolic Array Core Architecture Design for DNA Sequencer
MATEC Web of Conferences
Materials Science
Engineering
Chemistry
A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm
ISRN Bioinformatics
Efficient Online and Offline Testing of Embedded DRAMs
IEEE Transactions on Computers
Hardware
Architecture
Mathematics
Computational Theory
Theoretical Computer Science
Software
Virtual Systolic Array for QR Decomposition
Online and Offline Information for Omnichannel Retailing
Manufacturing and Service Operations Management
Management Science
Management
Operations Research
Strategy
Chain Architecture: An Efficient Hardware Solution for a Large Microphone Array System
