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Publications by Kris Tiri
Clock Tree Optimization in Synchronous CMOS Digital Circuits for Substrate Noise Reduction Using Folding of Supply Current Transients
Proceedings - Design Automation Conference
Control
Systems Engineering
Electronic Engineering
Simulation
Hardware
Computer Science Applications
Electrical
Architecture
Modeling
Changing the Odds Against Masked Logic
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
Related publications
Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits
Estimation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits
An Algorithm for Leakage Power Reduction Through IVC in CMOS VLSI Digital Circuits
International Journal of Computer Applications
Design Techniques for Gate-Leakage Reduction in CMOS Circuits
Leakage Current in Deep-Submicron Cmos Circuits
Journal of Circuits, Systems and Computers
Hardware
Electronic Engineering
Electrical
Architecture
Analysis of Clock Trees for Optimization Through Multi Point Clock Tree Synthesis
International Journal of Recent Technology and Engineering
Engineering
Management of Technology
Innovation
Investigation of Intermittent Resistive Faults in Digital CMOS Circuits
Journal of Circuits, Systems and Computers
Hardware
Electronic Engineering
Electrical
Architecture
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
