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Publications by Laurens Breyne
A DC-Coupled 50 Gb/S 0.064 pJ/bit Thin-Oxide Level Shifter in 28 Nm FDSOI CMOS
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Related publications
LAPA, a 5 Gb/S Modular Pseudo-LVDS Driver in 180 Nm CMOS With Capacitively Coupled Pre-Emphasis
A 40-Gb/S Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-Nm CMOS
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
A 28-Nm CMOS 1 v 3.5 GS/s 6-Bit DAC With Signal-Independent Delta-I Noise DfT Scheme
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
40-Gb/S 2:1 Multiplexer and 1:2 Demultiplexer in 120-Nm Standard CMOS
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
A Fully-Integrated 125-Gb/S 850-Nm CMOS Optical Receiver Based on a Spatially-Modulated Avalanche Photodetector
Optics Express
Optics
Atomic
Molecular Physics,
An Energy-Efficient 32-Bit Multiplier Architecture in 90-Nm CMOS
Intermodulation Linearity in High-K/Metal Gate 28 Nm RF CMOS Transistors
Electronics (Switzerland)
Control
Electronic Engineering
Signal Processing
Computer Networks
Systems Engineering
Hardware
Communications
Electrical
Architecture
A 10gs/S 8-Bit Current Steering DAC in 65nm CMOS Technology
CMOS Building Blocks for 10+Gb/S Clock Data Recovery Circuit
